1. Field of the Invention
The present invention relates to the general field of cache memory circuits.
2. Description of the Related Art
Cache memory circuits are well known in the art as memory circuitry which may enable optimal response to the needs of a high speed processor. Cache memories are usable as temporary storage of information, for example of information relatively recently used by the processor. Information in cache RAM may be stored based upon two principles, namely spatial locality and temporal locality. The principle of spatial locality is based upon the fact that when data is accessed at an address, there is an above average likelihood that the data which is next required will have an address close to that of the data which has just been accessed. By contrast, temporal locality is based upon the fact that there is an above average probability that data which has just been accessed will be accessed again shortly.
In one approach therefore, when an item of data is accessed, adjacent data is written to cache memory in anticipation of the need to access it, and in another, the item which is accessed is stored. A desirable approach is to do both.
There are many different cache configurations, ranging from direct-mapped cache memory to fully-associative cache memory.
Although the present invention is described in the context of a set-associative cache memory, is not envisaged that it be so limited, and the architecture described and the particular circuit details are equally applicable to other types of cache.
In a typical cache memory, there is provided a so-called xe2x80x9ctag memoryxe2x80x9d and a so-called xe2x80x9cdata memoryxe2x80x9d. Each entry in the tag memory has an associated entry in the data memory. The tag memory typically stores the most significant bits of an address at a position in the memory determined by the least significant bits of the address so that application of the least significant bits of the address to an address decoder causes the tag memory to output the stored most significant bits of an address. Comparison is then made between the output of the tag memory, namely the most significant bits of the stored address and the most significant bits of the address being sought. When identity occurs between the output of the tag memory and the address being sought, then there is said to be a hit in the tag memory. A line or entry in the data memory is associated with the access from the address decoder and a second output is made which consists of the data stored at an address. If there is a hit between the address applied to the cache and the tag information stored, then the contents of the data memory are output from the cache. If there is no hit, (this situation is termed a xe2x80x9cmissxe2x80x9d) then the contents of the data memory are not output.
According to the particular technique being used, a mechanism may exist for overwriting both the tag and data RAMs if no hit occurs.
It will be clear to those skilled in the art that timing difficulties exist in determining whether or not a hit has occurred, and in outputting the data from the data RAM upon the occurrence of a hit. For example, upon addressing a tag entry and the corresponding data entry, the tag information is output from the tag RAM and must then be compared with input address information and a decision reached as to whether or not identity exists. Only when the result of that decision has been validly determined can a gate be controlled to enable output of the data from the data RAM. The critical path is thus the tag RAM access.
A person skilled in the art will also be aware that memory sense amplifiers respond to differentials on bit lines or to potentials on bit lines to provide an output which corresponds to the information stored in the memory cells via bit lines, experience a delay after access to the memory cells of concern before those inputs have a sufficient potential difference to accurately sense the contents of the cell. This is due to the inherent capacitance and inductance of the bit lines. As a result, the sense amplifiers must be clocked at an instant which is sufficiently later than the memory cell access to ensure that the sense amplifier inputs are valid, and hence that the output of the sense amplifier will be valid. There is a further timing issue in that only at some interval after clocking of the sense amplifier-this interval being due to the inherent delay of the sense amplifier-the sense amplifier outputs will correspond to the memory cell contents. The outputs of the sense amplifier in a tag RAM typically form first inputs to a comparator, the comparator having second inputs formed by the most significant bits of the address concerned and further having an output fed to the above-mentioned gate. It will be appreciated by those skilled in the art that the comparator output should only indicate a hit when a tag hit is genuinely present or a miss when a tag miss is present. It is undesirable that the comparator output indicate a hit or miss merely because its inputs are not yet valid, because for example the sense amplifier providing those inputs has not yet settled or has not yet been enabled by the clock.
According to a first aspect of the invention there is provided a cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry and decision circuitry for selectively enabling said data RAM sense amplifier circuitry, said decision circuitry having a first input for stored tag data and a second input for address data, said decision circuitry having a first valid state when said tag data matches said address data and a second valid state different to said first valid state when said tag data differs from said address data, said decision circuitry having a control input for setting said decision circuitry to an invalid state different to said valid states, wherein said decision circuitry has first and second nodes, said nodes being at complementary logic levels in said valid output states and at a common potential in said invalid state.
Preferably said tag RAM sense amplifier circuitry has an enable input for receiving an enable signal, said cache memory further comprising timing circuitry having an input connected to said enable input and a first output connected to said control input of said decision circuitry, whereby said decision circuit attains one of said first and second valid states a first predetermined interval after application of an enable signal to said enable input of said tag RAM sense amplifier circuitry.
Advantageously said decision circuitry further comprises first current source circuitry for selectively applying a current to said first node when said address data differs from said stored tag data and second current source circuitry for applying a second current source to said second node and sensing circuitry having first and second sensing circuitry nodes, said sensing circuitry being responsive to a potential on said first and second nodes for establishing said first and second valid states on said first and second sensing circuitry nodes.
Conveniently said sensing circuitry comprises equalization circuitry responsive to said enable input of said tag RAM sense amplifier circuitry for selectively applying said common potential to said first and second sensing circuitry nodes.
Preferably, said sensing circuitry comprises a latch circuit connected between said first and second sensing circuitry nodes and selectively connectable to said first and second nodes via a gating circuit, said latch circuit and said gating circuit being activated by said control input.
Preferably again, said second current source circuitry is connected to a second output of said timing circuit, whereby said second current source is activated a second predetermined interval after said application of said enable signal. Conveniently, said first current source circuitry comprises a first transistor.
Advantageously, said tag RAM comprises a plurality of bit line pairs, each pair having an associated tag RAM sense amplifier and an associated first current source, each first current source comprising a respective first transistor, said first transistors being identical and of one polarity, said first current sources being connected between one said first node and a reference node, and said second current source circuitry comprising a said plurality of second transistors connected between said second node and said reference node, said second transistors being of said one polarity.
Conveniently, one of said second transistors has half the current carrying capability of said first transistors, and has a control gate connected to said second output of said timing circuitry.
Conveniently, the remaining second transistors have control gates connected to said reference node.
Advantageously, said timing circuitry comprises a first delay circuit having said enable input of said tag RAM sense amplifier circuitry as its input and said second output as its output and a second delay circuitry in series therewith, said second delay circuit comprising a plurality of third transistors connected in parallel between a timing node and said reference node, said third transistors being of said one polarity, and a fourth transistor of opposite polarity connected between said timing node and a supply rail, said timing node providing an output to said control input.
Advantageously again, said decision circuitry further comprises logic circuitry connected to said data RAM sense amplifier at an enable terminal thereof, said logic circuitry being responsive to said first and second sensing circuitry nodes and providing a first predetermined output for enabling said data RAM sense amplifier circuitry only in response to one of said valid states at said nodes.
Conveniently, said logic circuitry has a control input whereby said logic circuitry responds to a predetermined logic state at said control input to provide said predetermined output for enabling said data RAM sense amplifier circuitry in response to the other valid state.
Preferably said data RAM sense amplifier circuitry has differential input terminals and precharge and equalization circuitry for precharge and equalization of said differential input terminals, said cache memory further comprising OR circuitry connected to said first and second sensing circuitry nodes, and to said precharge and equalization circuitry for terminating precharge and equalization when said first and second sensing circuitry nodes change from said invalid state to one of said valid states.
Advantageously, said data RAM sense amplifier circuitry has an output for data stored by said data RAM, said output being at a high impedance state when said precharge and equalization circuitry is active.
Preferably, said tag RAM sense amplifier circuitry has first and second differential outputs, wherein said decision circuitry further comprises multiplexer circuitry having an output, said multiplexer circuitry having an input for said address data whereby said multiplexer circuitry passes the state at said first differential output when said address data is logic 1 and the state at said second differential output when said address data is logic 0.
Conveniently, said first current source circuitry responds to the output of said multiplexer circuitry.
According to a second aspect of the invention there is provided a method of operating a cache memory having a stored tag data, an input for address data, a data RAM, data RAM sense amplifier circuitry and decision circuitry for selectively enabling said data RAM sense amplifier circuitry, said decision circuitry having a first and a second node, the method comprising: sensing stored tag data; comparing said stored tag data with input address data; and setting said first and second nodes to a common potential, wherein said comparing step comprises providing a first logic level on the first node and a second opposite logic level on the second node in response to a match between said stored tag data and said input address data; and providing said second logic level on the first node and said second opposite logic level on the first node when said stored tag data differs from said address data.
Advantageously said step of sensing comprises providing an enable signal to said tag RAM sense amplifier circuitry and maintaining said common potential on said first and second nodes for a first predetermined interval after application of said enable signal.
Conveniently, said decision circuitry further has a sense node and a reference node, and said comparing step comprising: applying a reference current to said reference node, applying a current to said sense node when said input address data differs from said stored tag data after a second interval, applying the potentials on said reference and sense nodes to a latch circuit.
Preferably, said cache memory comprises a tag RAM and a tag RAM sense amplifier, having first and second differential outputs, wherein said comparing step further comprises selecting one of said differential outputs when said address data has a first logic value, and the other of said differential outputs when said address data has a second logic value opposite to said first logic value, and using the selected output to control application of said current to said sense node.
According to a third aspect of the present invention there is provided a cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry and decision circuitry for providing a read enable signal to a read enable terminal of said data RAM sense amplifier circuitry, said decision circuitry having a first input for stored tag data, a second input for address data and a pair of intermediate nodes, a first of said intermediate nodes being at logic 1 and the second being at logic 0 when said tag data matches said address data, the second of said intermediate nodes being at logic 1 and the first being at logic 0 when said tag data differs from said address data, said decision circuitry having a control input for setting said nodes to a common potential, wherein said decision circuitry further comprises logic circuitry being responsive to said first and second intermediate nodes and operable to provide a read enable signal to said read enable terminal only in response to a said match, wherein said logic circuitry has a control input and said logic circuitry responds to a predetermined logic state at said control input to provide said read enable signal to said read enable terminal whenever said intermediate nodes have complementary levels.
According to a fourth aspect of the present invention there is provided a method of operating a cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry having a read enable input, the method comprising: sensing stored tag data; comparing said sensed tag data with input address data; establishing a first circuit condition and maintaining said first circuit condition until a valid comparison is achieved and upon achieving a valid comparison: establishing a second circuit condition when a match is detected between said sensed tag data and said input address data establishing a third circuit condition when no match is detected, in response to said step of establishing said second condition: generating a read enable signal; and supplying said read enable signal to said read enable input, the method further comprising: determining an input at a control terminal to selectively provide said read enable signal to said read enable terminal responsive to said step of establishing said third condition.
According to a fifth aspect of the present invention there is provided a cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry and decision circuitry, the tag RAM sense amplifier circuitry having an enable input for receiving a sense amplifier enable signal, the decision circuitry having a first input for stored tag data, a second input for address data and a control input for enabling said decision circuitry, the data RAM sense amplifier circuitry having a disable input terminal and a read input terminal, said decision circuitry providing a data read signal to said read input terminal of said data RAM sense amplifier circuitry when a match exists between said stored tag data and said address data, the memory further comprising: timing circuitry responsive to said sense amplifier enable signal for maintaining a first level at said control input thereby holding an output of said decision circuitry in an inactive condition for a given period, and thereafter applying a second level at said control input, thereby allowing said output to become active; and logic circuitry sensing an active output of said decision circuitry for supplying a disabling signal to said disable input terminal, thereby disabling said data RAM sense amplifier circuitry until after said output of said decision circuitry becomes active.
According to a sixth aspect of the present invention there is provided a method of operating a cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry and decision circuitry, the tag RAM sense amplifier circuitry having an enable input for receiving a sense amplifier enable signal, the decision circuitry having a first input for stored tag data, a second input for address data and a control input for enabling said decision circuitry, the data RAM sense amplifier circuitry having a disable input terminal and a read input terminal, the method comprising: providing a disabling signal to said disable input terminal, thereby disabling said data RAM sense amplifier circuitry; maintaining a first level at said control input thereby holding an output of said decision circuitry in an inactive condition for a given period after said sense amplifier enable signal; thereafter applying a second level at said control input, thereby allowing said output to become active; sensing the output of said decision circuitry; in response to an active output, terminating supply of said disabling signal to said disable input terminal; and providing a data read signal to said read input terminal of said data RAM sense amplifier circuitry when a match exists between said stored tag data and said address data.